In the design of an integrated circuit device, it is typically useful to simulate functional modules of the device, such as memory (e.g. a cache), prior to building physical device samples, in order to ensure that in operation the device will comply with a specification. Accordingly, in the design process of an integrated circuit memory, bitcell models are used to simulate operation of physical bitcells of the memory. In the simulation process it is desirable to determine the extent of potential variability in the operation of a bitcell, so that the variability in bitcell operation can be accounted for in the design of the integrated circuit device.
One method of determining the variability of a bitcell includes simulating operation of the bitcell while randomly varying each of a number of component characteristics such as transistor threshold voltage, transistor channel length, and transistor channel width, for each transistor of the bitcell. However, this process can require an undesirable amount of time. For example, for a bitcell having 6 transistors with three component characteristics for each transistor, millions of simulations are run in order to determine bitcell variability, requiring hours or days of simulation time. Alternatively, the operation of the memory module can be simulated assuming that each component characteristic of the bitcell is at a specified worst-case variation from nominal values. However, these assumptions typically will not accurately reflect actual operating conditions of the memory module. Accordingly, an improved method for simulating operation of a bitcell would be desirable.